View M36W416TG_319295.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M36W416TG M36W416BG
16 Mbit (1Mb x16, Boot Block) Flash Memory and 4Mbit (256Kb x16) SRAM, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY s MULTIPLE MEMORY PRODUCT - 16 Mbit (1Mb x 16) Boot Block Flash Memory - 4 Mbit (256Kb x 16) SRAM s SUPPLY VOLTAGE - VDDF = VDDS = 2.7V to 3.3V - VDDQF = VDDS = 2.7V to 3.3V - VPPF = 12V for Fast Program (optional)
s s s
SRAM s 4 Mbit (256Kb x 16)
s s s
ACCESS TIME: 70ns LOW VDDS DATA RETENTION: 1.5V POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS
ACCESS TIME: 70ns, 85ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M36W416TG: 88CEh - Bottom Device Code, M36W416BG: 88CFh
Figure 1. Packages
FBGA
FLASH MEMORY s MEMORY BLOCKS - Parameter Blocks (Top or Bottom location) - Main Blocks
s
Stacked LFBGA66 (ZA) 12 x 8mm
PROGRAMMING TIME - 10s typical - Double Word Programming Option
s
BLOCK LOCKING - All blocks locked at Power up - Any combination of blocks can be locked - WPF for Block Lock-Down
s s s
AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK COMMON FLASH INTERFACE - 64 bit Security Code SECURITY - 64 bit user programmable OTP cells - 64 bit unique device identifier - One parameter block permanently lockable
s
s
November 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A18-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDDF and VDDS Supply Voltages.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDDQF and V DDS Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSSF and VSSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Stacked LFBGA66-12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline15 Table 7. Stacked LFBGA66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, Package Mechanical Data . 15 Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . . 16 Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package). 17
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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 FLASH DEVICE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FLASH SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10. Flash Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . 20 FLASH BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FLASH COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . 26 FLASH BLOCK LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VPP Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 13. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . 33 Figure 14. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . 34 Table 20. Flash Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . 35 Figure 15. Flash Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 21. Flash Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SRAM SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 16. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL . . . 39 Figure 18. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 22. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 20. SRAM Write AC Waveforms, WS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 21. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . 43 Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low . . . . . . . . . . . . . 43 Table 23. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 24. SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled . . 45 Table 24. SRAM Low VDDS Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 25. Top Boot Block Addresses, M36W416TG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 26. Bottom Boot Block Addresses, M36W416BG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 27. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 28. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 29. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 31. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 32. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 25. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 27. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 54 Figure 28. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 30. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 59 Table 33. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 34. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 35. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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M36W416TG, M36W416BG
SUMMARY DESCRIPTION The M36W416TG is a low voltage Multiple Memory Product which combines two memory devices; a 16 Mbit boot block Flash memory and a 4 Mbit SRAM. Recommended operating conditions do not allow both the Flash memory and the SRAM memory to be active at the same time. The memory is offered in a Stacked LFBGA66 (12x8mm, 8 x 8 active ball, 0.8 mm pitch) package and is supplied with all the bits erased (set to `1'). Figure 2. Logic Diagram
VDDQF VDDF 20 A0-A19 EF GF WF RPF WPF E1S E2S GS WS UBS LBS M36W416TG M36W416BG VDDS
Table 1. Signal Names
A0-A17 A18-A19 DQ0-DQ15 VDDF VDDQF VPPF VSSF VDDS Flash and SRAM Address Inputs Address Inputs for Flash Chip only Data Input/Output Flash Power Supply Flash Power Supply for I/O Buffers Flash Optional Supply Voltage for Fast Program & Erase Flash Ground SRAM Power Supply SRAM Ground Not Connected Internally
VPPF 16 DQ0-DQ15
VSSS NC
Flash control functions EF GF WF RPF WPF Chip Enable input Output Enable input Write Enable input Reset input Write Protect input
SRAM control functions E1S, E2S GS WS UBS Chip Enable inputs Output Enable input Write Enable input Upper Byte Enable input Lower Byte Enable input
VSSF
VSSS
AI07940
LBS
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#1
#2
1
2
3
4
5
6
7
8
#3
#4
A A12 NC
NC
NC
NC
A11
A15 A13 VSSF VDDQF
A14
NC
B DQ14 DQ7
A16
A8 A9 DQ15 WS
A10
C
WF DQ4
NC
DQ13
DQ6
DQ5
D
VSSS
RPF DQ12 E2S
VDDS
VDDF
Figure 3. LFBGA Connections (Top view through package)
E WPF VPPF A19 DQ11
DQ10
DQ2
DQ3
F
LBS
UBS GS
DQ9
DQ8
DQ0
DQ1
G
A18
A17 A7
A6
A3
A2
A1
E1S
H
NC
NC
NC
A5
A4
A0
EF
VSSF
GF
NC
NC
NC
M36W416TG, M36W416BG
AI90254
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SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (WF) signals, while the SRAM is accessed through two Chip Enable (ES) and Write Enable (WS) signals. Address Inputs (A18-A19). Addresses A18-A19 are inputs for the Flash component only. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (WF) signals Data Inputs/Outputs (DQ0-DQ15). The Data I/ O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF). The Chip Enable input activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VIL and Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable controls the data outputs during the Bus Read operation of the Flash memory. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, EF, or Write Enable, WF, whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at V IH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 6, Read Protection Register and Protection Register Lock). Flash Reset (RPF). The Reset input provides a hardware reset of the Flash memory. When Reset is at V IL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked state. When Reset is at V IH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition
of Chip Enable or a change of the address is required to ensure valid data outputs. SRAM Chip Enable (E1S, E2S). The Chip Enable inputs activate the SRAM memory control logic, input buffers and decoders. E1 S at V IH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S or E2S can also be used to control writing to the SRAM memory array, while WS remains at V IL. It is not allowed to set EF at VIL and, E1S at VIL or E2 S at VIL at the same time. SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array. W S is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM memory. GS is active low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. proVDDF and VDDS Supply Voltages. VDDF vides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQF and V DDS Supply Voltage (2.7V to 3.3V). VDDQF provides the power supply for the Flash memory I/O pins and VDDS provides the power supply for the SRAM control pins. This allows all Outputs to be powered independently of the Flash core power supply, VDDF. VDDQF can be tied to VDDS. VPPF Program Supply Voltage. VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VDDF and the Program Supply Voltage VPPF can be applied in any order. If V PPF is kept in a low voltage range (0V to 3.6V) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPPF > VPP1 enables these functions (see Table 6, DC Characteristics for the relevant values). V PPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPPF is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition V PPF must be stable until the Program/Erase algorithm is completed (see Table 19 and 20).
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VSSF and VSSS Ground. VSSF and VSSS are the ground reference for all voltage measurements in the Flash and SRAM chips, respectively. Note: Each device in a system should have V DDF, VDDQF and VPPF decoupled with a 0.1F capacitor close to the pin. See Figure 9, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required V PPF program and erase currents.
FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip enable inputs: EF for the Flash memory and E1S and E2S for the SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be in active mode at the same time. The most common example is Figure 4. Functional Block Diagram
VDDF
simultaneous read operations on the Flash and the SRAM which would result in a data bus contention. Therefore it is recommended to put the SRAM in the high impedance state when reading the Flash and vice versa (see Table 2 Main Operation Modes for details).
VDDQF
VPPF
EF GF WF RPF WPF A18-A19 A0-A17 Flash Memory 16 Mbit (x16)
VDDS
VSSF
DQ0-DQ15
E1S E2S GS WS UBS LBS SRAM 4 Mbit (x16)
VSSS
AI07941
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Table 2. Main Operation Modes
Operation Mode Read Write Flash Memory Block Locking Standby Reset Output Disable EF VIL VIL VIL VIH X VIL GF VIL VIH X X X VIH WF VIH VIL X X X VIH RPF VIH VIH VIH VIH VIL VIH WPF X X VIL X X X VPPF Don't care VDDF or VPPFH Don't care Don't care Don't care Don't care VIL VIL VIL VIL VIL VIL VIH Any Flash mode is allowable X VIH X VIL VIL VIL E1S E2S GS WS UBS LBS DQ7-DQ0 DQ15-DQ8 Data Output Data Input X Hi-Z Hi-Z Hi-Z Data out Word Read Data out Hi-Z Hi-Z Data out
SRAM must be disabled SRAM must be disabled SRAM must be disabled Any SRAM mode is allowed Any SRAM mode is allowed Any SRAM mode is allowed VIH VIH VIH VIH VIH VIH VIL X VIL X VIH VIH VIH VIL VIL VIL X X X X X X X VIH VIH VIH VIH VIH VIH VIL VIL VIL X X X X VIH VIH VIH VIL VIH VIL VIL VIH VIL X VIH X VIH VIL VIH VIL VIL VIL VIH VIL VIL VIH X VIH X VIH VIL VIL VIH
Flash must be disabled Read Flash must be disabled Flash must be disabled Flash must be disabled Write SRAM Flash must be disabled Flash must be disabled Standby/ Power Down Data Retention Output Disable
Data in Word Write Data in Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data in
Any Flash mode is allowable Any Flash mode is allowable Any Flash mode is allowable Any Flash mode is allowable
Note: X = Don't care = VIL or VIH, VPPFH = 12V 5%.
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG VIO VDDF, VDDQF VPPF VDDS Parameter Min Ambient Operating Temperature (1) Temperature Under Bias Storage Temperature Input or Output Voltage Flash Supply Voltage Program Voltage SRAM Supply Voltage -40 -40 -55 -0.5 -0.5 -0.6 -0.5 Max 85 125 150 VDDQF +0.3 3.8 13 3.8 C C C V V V V Unit
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Depends on range.
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M36W416TG, M36W416BG
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 4, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 4. Operating and AC Measurement Conditions
SRAM Parameter Min VDDF Supply Voltage VDDQF = VDDS Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages - 2.7 - 40 30 1V/ns 0 to VDDQF VDDQF/2 70 Max - 3.3 85 Min 2.7 2.7 - 40 50 5ns 0 to VDDQF VDDQF/2 V V Flash Memory 70/85 Max 3.3 3.3 85 V V C pF Units
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VDDQF
VDDQ VDDQ/2 0V
AI90258
VDDQF VDDF 25k DEVICE UNDER TEST 0.1F 0.1F CL 25k
Note: VDDQ means VDDQF = VDDS
CL includes JIG capacitance
AI90259
Table 5. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V, f=1 MHz VOUT = 0V, f=1 MHz Typ Max 12 15 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 6. DC Characteristics
Symbol ILI Parameter Input Leakage Current Device Flash & SRAM Flash ILO Output Leakage Current SRAM Flash Test Condition 0V VIN VDDQF 0V VOUT VDDQF 0V VOUT VDDQF, SRAM Outputs Hi-Z EF = VDDQF 0.2V RPF = VDDQ 0.2V E1S VDDS - 0.2V VIN VDDS - 0.2V or VIN 0.2V f = fmax (A0-A17 and DQ0DQ15 only) f = 0 (GS, WS, UBS and LBS) E1S VDDS - 0.2V VIN VDDS - 0.2V or VIN 0.2V, f = 0 15 Min Typ Max 1 10 1 50 Unit A A A A
IDDS
VDD Standby Current SRAM
7
15
A
7
15 5.5 1.5 10 10 10 5 5
15
50 12 3 20 20 20 20 20 50 400 5 5 10 5
A
A mA mA mA mA mA mA mA A A A A mA mA
IDDD
Supply Current (Reset)
Flash
RPF = VSSF 0.2V f = fmax = 1/AVAV, VIN 0.2V, IOUT = 0 mA f = 1MHz, VIN 0.2V, IOUT = 0 mA
IDD
Supply Current
SRAM
IDDR
Supply Current (Read)
Flash
EF = VIL, GF = VIH, f = 5 MHz Program in progress VPPF = 12V 5%
IDDW
Supply Current (Program)
Flash Program in progress VPPF = VDDF Erase in progress VPPF = 12V 5%
IDDE
Supply Current (Erase)
Flash Erase in progress VPPF = VDDF
IDDES IPP1 IPP2 IPPR
Supply Current (Program/Erase Suspend) Program Current (Read or Standby) Program Current (Read or Standby) Program Current (Reset)
Flash Flash Flash Flash
EF = VDDQF 0.2V, Erase suspended VPPF > VDDF VPPF VDDF RPF = VSSF 0.2V VPPF = 12V 0.5V Program in progress
IPPW
Program Current (Program)
Flash VPPF = VDDF Program in progress
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Symbol Parameter Device Test Condition VPPF = 12V 0.5V Erase in progress IPPE Program Current (Erase) Flash VPPF = VDDF Erase in progress Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) Program Voltage (Program and Erase lockout) VDDF Supply Voltage (Program and Erase lockout) Flash & SRAM Flash & SRAM Flash & SRAM Flash & SRAM VDDQF = VDDS 2.7V VDDQF = VDDS 2.7V VDDQF = VDDS = VDD min IOL = 100A VDDQF = VDDS = VDD min IOH = -100A VDDQ -0.1 1.65 3.6 5 A Min Typ Max 10 Unit mA
VIL
-0.3 0.7 VDDQF
0.8
VDDQF +0.3 0.1
V
V V V
VIH
VOL VOH
VPP1
Flash
V
VPPFH
Flash
11.4
12.6
V
VPPLK
Flash
1
V
VLKO
Flash
2
V
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M36W416TG, M36W416BG
PACKAGE MECHANICAL Figure 7. Stacked LFBGA66-12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline
D D2 D1
SE E E1 BALL "A1"
b
e
FE A
FD
SD
e A2 A1
ddd
BGA-Z12
Note: Drawing is not to scale.
Table 7. Stacked LFBGA66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 D2 ddd E E1 e FD FE SD SE 8.000 5.600 0.800 1.600 1.200 0.400 0.400 - - - - - - - 0.400 12.000 5.600 8.800 0.300 - - - 0.300 1.100 0.500 - - - 0.100 - - - - - - - 0.3150 0.2205 0.0315 0.0630 0.0472 0.0157 0.0157 - - - - - - - 0.0157 0.4724 0.2205 0.3465 0.0118 - - - millimeters Typ Min Max 1.400 0.0118 0.0433 0.0197 - - - 0.0039 - - - - - - - Typ inches Min Max 0.0551
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Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)
#1
#2
1
2
3
4
5
6
7
8
#3
#4
G
C
D
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H
A
B
E
F
AI90273
M36W416TG, M36W416BG
Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)
END POINT
START POINT
#1
#2
1
2
3
4
5
6
7
8
#3
#4
G
C
D
H
A
B
E
F
AI90274
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PART NUMBERING Table 8. Ordering Information Scheme
Example: Device Type M36 = MMP (Flash + SRAM) Operating Voltage W = VDDF = 2.7V to 3.3V, VDDS = VDDQF = 2.7V to 3.3V SRAM Chip Size & Organization 4 = 4 Mbit (256Kb x 16 bit) Flash Chip Size & Organization 16 = 16 Mbit (x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot SRAM Component G = 4Mb, 0.16m, 70ns, 3V Speed 70 = 70ns 85 = 85ns Package ZA = LFBGA66: 12x8mm, 0.8mm pitch Temperature Range 1 = 0 to 70C 6 = -40 to 85C Option T = Tape & Reel packing M36W416 T G 70 ZA 6 T
Devices are shipped from the factory with the memory content bits erased to '1'. Table 9. Daisy Chain Ordering Scheme
Example: Device Type M36W416TG Daisy Chain -ZA = LFBGA66: 12x8mm, 0.8mm pitch Option T = Tape & Reel Packing M36W416TG -ZA T
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M36W416TG, M36W416BG
FLASH DEVICE
The M36W416TG contains one 16 Mbit Flash memory. This section describes how to use the Flash device and all signals refer to the Flash device.
FLASH SUMMARY DESCRIPTION The Flash Memory is a 16 Mbit (1 Mbit x 16) nonvolatile device that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. VDDQF is used to drive the I/O pin down to 1.65V. An optional 12V VPPF power supply is provided to speed up customer programming. The device features an asymmetrical blocked architecture with an array of 39 blocks: 8 Parameter Blocks of 4 KWords and 31 Main Blocks of 32 KWords. The M36W416TG has the Parameter Blocks at the top of the memory address space while the M36W416BG locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 10, Block Addresses. The Flash Memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPPF VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up.
Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 128 bit Protection Register and a Security Block to increase the protection of a system design. The Protection Register is divided into two 64 bit segments, the first one contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 11, shows the Flash Security Block Memory Map. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
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Figure 10. Flash Block Addresses
Top Boot Block Addresses Bottom Boot Block Addresses
FFFFF 4 KWords FF000 Total of 8 4 KWord Blocks F8FFF 4 KWords F8000 F7FFF 32 KWords F0000
FFFFF 32 KWords F8000 F7FFF 32 KWords F0000 Total of 31 32 KWord Blocks
0FFFF 32 KWords 08000 07FFF 4 KWords Total of 31 32 KWord Blocks 07000 Total of 8 4 KWord Blocks 00FFF 32 KWords 4 KWords 00000
0FFFF 32 KWords 08000 07FFF 00000
AI90256
Note: Also see Appendix A, Tables 25 and 26 for a full listing of the Flash Block Addresses.
Figure 11. Flash Security Block and Protection Register Memory Map
PROTECTION REGISTER SECURITY BLOCK 88h User Programmable OTP 85h 84h Parameter Block # 0 81h 80h Protection Register Lock 2 1 0 Unique device number
AI07905
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FLASH BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2, Main Operation Modes, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 12, Flash Read Mode AC Waveforms, and Table 18, Flash Read AC Characteristics, for details of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V IL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figures 13 and 14, Flash Write AC Waveforms, and Tables 19 and 20, Flash Write AC
Characteristics, for details of the timing requirements. Output Disable. The data outputs are high impedance when the Output Enable is at V IH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Automatic Standby. Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs will still output data if a bus Read operation is in progress. Reset. During Reset mode when Output Enable is Low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at V IL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to V SS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
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M36W416TG, M36W416BG
FLASH COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Program/Erase states. See Appendix 29, Table 33, Write State Machine Current/Next, for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Reset or whenever V DD is lower than VLKO . Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 10, Commands, in conjunction with the text descriptions below. Read Memory Array Command The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register's contents. Subsequent Bus Read operations read the Status Register at any address, until another command is issued. See Table 17, Status Register Bits, for details on the definitions of the bits. The Read Status Register command may be issued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will automatically output the content of the Status Register. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or the Protection and Lock Register. See Tables 11, 12 and 13 for the valid address. Read CFI Query Command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 27, 28, 29, 30, 31 and 32 for details on the information contained in the Common Flash Interface memory area. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. s The first bus cycle sets up the Erase command. s The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 28, Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command. Program Command The memory array can be programmed word-byword. Two bus write cycles are required to issue the Program Command. s The first bus cycle sets up the Program command. s The second latches the Address and the Data to be written and starts the Program/Erase Controller. During Program operations the memory will accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program
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operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 25, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when V PP is not at VPPFH. The command can be executed if VPP is below VPPFH but the result is not guaranteed. Three bus write cycles are necessary to issue the Double Word Program command. s The first bus cycle sets up the Double Word Program Command. s The second bus cycle latches the Address and the Data of the first word to be written. s The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 26, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command. Clear Status Register Command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to `0' when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Block Lock, Block Lock-Down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 27, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 29, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register. See Appendix C, Figure 27, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 29, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 64 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. s The first bus cycle sets up the Protection Register Program command. s The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Protection Lock Register protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block (see Figure 11, Flash Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection
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Register and/or the Security Block is not reversible. The Protection Register Program cannot be suspended. See Appendix C, Figure 31, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the Protection Register Program command. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 16 shows the protection status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Unlock Command The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Blocks Unlock command. s The first bus cycle sets up the Block Unlock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 16 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Lock-Down Command A locked block cannot be Programmed or Erased, or have its protection status changed when WP F is low, V IL. When WPF is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 16 shows the protection status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation.
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Table 10. Flash Commands
Bus Write Operations Commands No. of Cycles 1st Cycle Bus Op.
Write Write Write Write Write Write Write Write Write Write Write Write Write Write
2nd Cycle Data
FFh 70h 90h 98h 20h 40h or 10h 30h 50h B0h D0h 60h 60h 60h C0h Write Write Write Write
3nd Cycle Data
Data Status Register Signature Query D0h Data Input Data Input Write Addr 2 Data Input
Addr
X X X X X X X X X X X X X X
Bus Op.
Read Read Read Read Write Write Write
Addr
Read Addr X Signature Addr (2) CFI Addr Block Addr Addr Addr 1
Bus Op.
Addr
Data
Read Memory Array Read Status Register Read Electronic Signature Read CFI Query Erase Program Double Word Program(3) Clear Status Register Program/Erase Suspend Program/Erase Resume Block Lock Block Unlock Block Lock-Down Protection Register Program
1+ 1+ 1+ 1+ 2 2 3 1 1 1 2 2 2 2
Block Address Block Address Block Address Address
01h D0h 2Fh Data Input
Note: 1. X = Don't Care. 2. The signature addresses are listed in Tables 11, 12 and 13. 3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.
Table 11. Read Electronic Signature
Code Manufacture. Code M36W416TG Device Code M36W416BG
Note: RP F = VIH.
Device
EF VIL VIL VIL
GF VIL VIL VIL
WF VIH VIH VIH
A0 VIL VIH VIH
A1 VIL VIL VIL
A2-A7 0 0 0
A8-A19 Don't Care Don't Care Don't Care
DQ0-DQ7 20h CEh CFh
DQ8-DQ15 00h 88h 88h
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Table 12. Read Block Lock Signature
Block Status Locked Block Unlocked Block Locked-Down Block EF VIL VIL VIL GF VIL VIL VIL WF VIH VIH VIH A0 VIL VIL VIL A1 VIH VIH VIH A2-A7 0 0 0 A8-A11 A12-A19 DQ0 1 0 X (1) DQ1 0 0 1 DQ2-DQ15 00h 00h 00h
Don't Care Block Address Don't Care Block Address Don't Care Block Address
Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.
Table 13. Read Protection Register and Lock Register
Word Lock Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 EF VIL VIL VIL VIL VIL VIL VIL VIL VIL GF VIL VIL VIL VIL VIL VIL VIL VIL VIL WF A0-A7 VIH VIH VIH VIH VIH VIH VIH VIH VIH 80h 81h 82h 83h 84h 85h 86h 87h 88h A8-A19 Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care DQ0 0 ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ1 OTP Prot. data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ2 Security prot. data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ3-DQ7 DQ8-DQ15 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data
Table 14. Program, Erase Times and Program/Erase Endurance Cycles
M36W416TG Parameter Word Program Double Word Program Main Block Program VPP = VDD VPP = 12V 5% Parameter Block Program VPP = VDD VPP = 12V 5% Main Block Erase VPP = VDD VPP = 12V 5% Parameter Block Erase VPP = VDD Program/Erase Cycles (per Block) 100,000 0.8 10 s cycles 1 0.8 10 10 s s 0.04 1 4 10 s s 0.32 0.02 5 4 s s Test Conditions Min VPP = VDD VPP = 12V 5% VPP = 12V 5% Typ 10 10 0.16 Max 200 200 5 s s s Unit
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FLASH BLOCK LOCKING The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. s Lock/Unlock - this first level allows softwareonly control of block locking.
s
Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
s
The lock status of each block can be set to Locked, Unlocked, and Lock-Down. Table 16, defines all of the possible protection states (WPF, DQ1, DQ0), and Appendix C, Figure 30, shows a flowchart for the locking operations. Reading a Block's Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 12, will output the lock status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate
software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their lock status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WPF input pin. When WPF=0 (V IL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WPF=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while WPF remains high. When WP F is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WPF was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the protection status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D, Command Interface and Program/Erase Controller State, for detailed information on which commands are valid during erase suspend.
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Table 15. Block Lock Status
Item Block Lock Configuration Block is Unlocked xx002 Block is Locked Block is Locked-Down DQ0=1 DQ1=1 Address Data LOCK DQ0=0
Table 16. Protection Status
Current Protection Status(1) (WPF, DQ1, DQ0) Current State 1,0,0 1,0,1
(2)
Next Protection Status(1) (WPF, DQ1, DQ0) After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WPF transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
Program/Erase Allowed yes no yes no yes no no
1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1
Note: 1. The protection status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status. 3. A WPF transition to V IH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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FLASH STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, refer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 17, Status Register Bits. Refer to Table 17 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High . During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to `1'), the Program/ Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V PP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the V PP pin was sampled at a valid voltage; when the V PP Status bit is High (set to `1'), the VPP pin has a voltage that is below the V PP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the V PP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended. When the Program Suspend Status bit is High (set to `1'), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Pro-
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gram/Erase Controller Status bit is High (Program/ Erase Controller inactive). Bit 2 is set within 5s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to Appendix C, Flowcharts and Pseudo Codes, for using the Status Register.
Table 17. Status Register Bits
Bit 7 Name P/E.C. Status '0' '1' 6 Erase Suspend Status '0' '1' 5 Erase Status '0' '1' 4 Program Status '0' '1' 3 VPP Status '0' '1' 2 Program Suspend Status '0' '1' 1 0 Block Protection Status '0' Reserved No operation to protected blocks In Progress or Completed Program/Erase on protected Block, Abort Program Success VPP Invalid, Abort VPP OK Suspended Erase Success Program Error In progress or Completed Erase Error Busy Suspended Logic Level '1' Ready Definition
Note: Logic level '1' is High, '0' is Low.
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Figure 12. Flash Read Mode AC Waveforms
tAVAV A0-A19 tAVQV EF tELQV tELQX GF tGLQV tGLQX DQ0-DQ15 VALID tGHQX tGHQZ tEHQX tEHQZ VALID tAXQX
ADDR. VALID CHIP ENABLE
OUTPUTS ENABLED
DATA VALID
STANDBY
AI07906
Table 18. Flash Read AC Characteristics
Flash Symbol tAVAV tAVQV tAXQX (1) tEHQX (1) tEHQZ (1) tELQV (2) tELQX (1) tGHQX (1) tGHQZ (1) tGLQV (2) tGLQX (1) Alt tRC tACC tOH tOH tHZ tCE tLZ tOH tDF tOE tOLZ Parameter 70 Address Valid to Next Address Valid Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Min Max Min Min Max Max Min Min Max Max Min 70 70 0 0 20 70 0 0 20 20 0 85 85 85 0 0 20 85 0 0 20 20 0 ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. GF may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV.
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PROGRAM OR ERASE tAVAV VALID tAVWH tWHAX tWHEH tWHWL tWHGL tWLWH tWHEL tWHDX COMMAND CMD or DATA STATUS REGISTER tELQV tWPHWH tQVWPL tVPHWH tQVVPL CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI07907
M36W416TG, M36W416BG
A0-A19
EF
tELWL
GF
WF
tDVWH
Figure 13. Flash Write AC Waveforms, Write Enable Controlled
DQ0-DQ15
WPF
VPPF
SET-UP COMMAND
M36W416TG, M36W416BG
Table 19. Flash Write AC Characteristics, Write Enable Controlled
Flash Symbol tAVAV tAVWH tDVWH tELWL tELQV tQVVPL (1,2) tQVWPL tVPHWH (1) tWHAX tWHDX tWHEH tWHEL tWHGL tWHWL tWLWH tWPHWH tWPH tWP tVPS tAH tDH tCH Alt tWC tAS tDS tCS Write Cycle Time Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Valid to VPPF Low Output Valid to Write Protect Low VPPF High to Write Enable High Write Enable High to Address Transition Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Output Enable Low Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Protect High to Write Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 70 0 0 200 0 0 0 25 20 25 45 45 85 85 45 45 0 85 0 0 200 0 0 0 25 20 25 45 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).
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PROGRAM OR ERASE tAVAV VALID tAVEH tEHAX tEHWH tEHEL tEHGL tELEH tEHDX COMMAND tWPHEH CMD or DATA STATUS REGISTER tQVWPL tELQV tVPHEH tQVVPL CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI07908
A0-A19
M36W416TG, M36W416BG
WF
tWLEL
GF
EF
tDVEH
Figure 14. Flash Write AC Waveforms, Chip Enable Controlled
DQ0-DQ15
WPF
VPPF
POWER-UP AND SET-UP COMMAND
M36W416TG, M36W416BG
Table 20. Flash Write AC Characteristics, Chip Enable Controlled
Flash Symbol tAVAV tAVEH tDVEH tEHAX tEHDX tEHEL tEHGL tEHWH tELEH tELQV tQVVPL (1,2) tQVWPL tVPHEH (1) tWLEL tWPHEH tVPS tCS tWH tCP Alt tWC tAS tDS tAH tDH tCPH Write Cycle Time Address Valid to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Data Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Output Valid Output Valid to VPPF Low Data Valid to Write Protect Low VPPF High to Chip Enable High Write Enable Low to Chip Enable Low Write Protect High to Chip Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 0 25 25 0 45 70 0 0 200 0 45 85 85 45 45 0 0 25 25 0 45 85 0 0 200 0 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).
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Figure 15. Flash Power-Up and Reset AC Waveforms
WF, EF,GF
tPHWL tPHEL tPHGL
tPHWL tPHEL tPHGL
RPF tVDHPH VDDF, VDDQF Power-Up Reset
AI07909b
tPLPH
Table 21. Flash Power-Up and Reset AC Characteristics
Flash Symbol Parameter Test Condition 70 tPHWL tPHEL tPHGL tPLPH(1,2) tVDHPH(3) During Program and Erase others Reset Low to Reset High Supply Voltages High to Reset High Min Min Min Min 50 30 100 50 85 50 30 100 50 s ns ns s Unit
Reset High to Write Enable Low, Chip Enable Low, Output Enable Low
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RPF in order to allow proper CPU initialization during power up or reset.
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SRAM DEVICE
This section describes how to use the SRAM and all signals refer to it.
SRAM SUMMARY DESCRIPTION The SRAM is a 4 Mbit asynchronous random access memory which features super low voltage operation and low current consumption with an access time of 70 ns under all conditions. The Figure 16. SRAM Logic Diagram
DATA IN DRIVERS
memory operations can be performed using a single low voltage supply, 2.7V to 3.3V, which is the same as the Flash component's voltage supply.
ROW DECODER
A0-A10
256Kb x 16 RAM Array 2048 x 2048
SENSE AMPS
DQ0-DQ7 DQ8-DQ15
COLUMN DECODER
A11-A17
UBS WS GS LBS
POWER-DOWN CIRCUIT
UBS LBS
E1S E2S
AI07939
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SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at V IL, Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at VIH, and one or both of the Byte Enable inputs, UBS and LBS is/are at VIL. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at tAVQV (see Table 22, Figures 17 and 18). Write. Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever W S and E1S are at VIL, and E2S is at VIH. Either the Chip Enable inputs, E1S and E2S, or the Write Enable input, W S, must be deasserted during address transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2 S is at VIH and WS is at VIL. The data is latched on the falling edge of E1S, the rising edge of E2S or the falling edge of W S, whichever occurs last. The Write cycle is terminated on the rising edge of
E1S, the rising edge of W S or the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S=VIL, E2S=VIH and GS=VIL), then WS will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. The Data input must be valid for t DVWH before the rising edge of Write Enable, for t DVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HAX or tE2LAX (see Table 23, Figures 20, 21, 22 and 23). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which invokes an automatic standby mode (see Table 22, Figure 19). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1 S at VIH or E2S at V IL. It is also possible when UBS and LBS are at VIH. Data Retention. The SRAM data retention performance as VDDS goes down to VDR are described in Table 24 and Figure 24. In E1S controlled data retention mode, the minimum standby current mode is entered when and E2S 0.2V or E1S VDDS - 0.2V E2S VDDS - 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2 S 0.2V. Output Disable. The data outputs are high impedance when the Output Enable, G S, is at VIH with Write Enable, W S, at VIH.
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Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V IL
tAVAV A0-A17 tAVQV tAXQX DQ0-DQ15 DATA VALID DATA VALID VALID
AI07942
Note: E1S = Low, E2S = High, GS = Low, WS = High.
Figure 18. SRAM Read AC Waveforms, GS Controlled
tAVAV A0-A17 tE1LQV E1S tE1LQX tE2HQV E2S tE2HQX tBLQV UBS, LBS tBLQX tGLQV GS tGLQX DQ0-DQ15 DATA VALID
AI07943
VALID tE1HQZ
tE2LQZ
tBHQZ
tGHQZ
Note: Write Enable (WS) = High. Address Valid prior to or at the same time as E1 S, UBS and LBS going Low.
Figure 19. SRAM Standby AC Waveforms
E1S
E2S IDD tPU 50% tPD
AI07913
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Table 22. SRAM Read AC Characteristics
SRAM Symbol tAVAV tAVQV tAXQX tBHQZ tBLQV tBLQX tE1LQV tE2HQV tE1LQX tE2HQX tE1HQZ tE2LQZ tGHQZ tGLQV tGLQX tPD (1) tPU (1) Alt tRC tACC tOH tBHZ tAB tBLZ tACS1 tCLZ1 tHZCE tOHZ tOE tOLZ Read Cycle Time Address Valid to Output Valid Address Transition to Output Transition UBS, LBS Disable to Hi-Z Output UBS, LBS Access Time UBS, LBS Enable to Low-Z Output Chip Enable 1 Low or Chip Enable 2 High to Output Valid Chip Enable 1 Low or Chip Enable 2 High to Output Transition Chip Enable High or Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable 1 High or Chip Enable 2 Low to Power Down Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 5 70 10 25 25 35 5 70 10 25 70 Parameter Min 70 70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only. Not 100% tested.
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Figure 20. SRAM Write AC Waveforms, WS Controlled
tAVAV A0-A17 VALID tAVWH tE1LWH E1S tWHAX
E2S tE2HWH tAVWL WS tBLWH UBS, LBS tWLWH
GS tGHQZ DQ0-DQ15 tDVWH tWHDZ
Note 2
INPUT VALID
AI07944
Note: WS, E1S, E2S, UB S and/or LB S must be asserted to initiate a write cycle. Output Enable (G S) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. The I/O pins are in output mode and input signals must not be applied.
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Figure 21. SRAM Write AC Waveforms, E1S Controlled
tAVAV A0-A17 VALID tAVE1H tAVE2L tAVE1L E1S tE1LE1H tE1HAX
E2S tAVE2H tE2HE2L tWLE1H tWLE2L WS tBLE1H tBLE2L UBS, LBS tE2LAX
GS tGHQZ DQ0-DQ15 tDVE1H tDVE2L tE1HDZ tE2LDZ
Note 3
INPUT VALID
AI07945
Note: 1. WS, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. 3. The I/O pins are in output mode and input signals must not be applied.
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Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low
tAVAV A0-A17 VALID tAVWH tE1LWH tE2HWH E1S tWHAX
E2S
tBLWH UBS, LBS tAVWL WS tWHQX tWLQZ DQ0-DQ15 tDVWH INPUT VALID
AI07946
tWLWH
tWHDZ
Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
Figure 23. SRAM Write Cycle Waveform, UBS and LB S Controlled, GS Low
tAVAV A0-A17 VALID tAVBH tE1LBH tE2HBH E1S
E2S tAVBL UBS, LBS tWLBH WS tDVBH DQ0-DQ15 INPUT VALID
AI07947
tBLBH
tBHAX
tBHDZ
Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
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Table 23. SRAM Write AC Characteristics
SRAM Symbol tAVAV tAVE1L, tAVE2H, tAVWL, tAVBL tAVE1H, tAVE2L tAVWH tBLWH tBLE1H tBLE2L tAVBH tBLBH tDVE1H, tDVE2L, tDVWH tDVBH tE1HAX, tE2LAX, tWHAX tBHAX tE1HDZ , tE2LDZ, tWHDZ tBHDZ tE1LE1H, tE1LBH tE1LWH tE2HE2L, tE2HBH, tE2HWH tGHQZ tWHQX tWLBH tWLQZ tWLWH tWLE1H tWLE2L Alt tWC Write Cycle Time Parameter Min 70 Max ns Unit
tAS
Address Valid to Beginning of Write
0
ns
tAW tAW
Address Valid to Chip Enable 1 Low or Chip Enable 2 High Address Valid to Write Enable High
60 60
ns ns
tBW
UBS, LBS Valid to End of Write
60
ns
tBW
UBS, LBS Low to UBS, LBS High
60
ns
tDW
Input Valid to End of Write
30
ns
tWR
End of Write to Address Change
0
ns
tHD
Address Transition to End of Write
0
ns
tCW1
Chip Enable 1 Low to End of Write
60
ns
tCW2 tGHZ tDH tWP tWHZ tWP
Chip Enable 2 High to End of Write Output Enable High to Output Hi-Z Write Enable High to Input Transition Write Enable Low to UBS, LBS High Write Enable Low to Output Hi-Z Write Enable Pulse Width
60 25 5 50 25 50
ns ns ns ns ns ns
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Figure 24. SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled
DATA RETENTION MODE VDDS VDDS (min) tCDR tR VDDS (min)
E1S or UBS, LBS
AI07918
Table 24. SRAM Low VDDS Data Retention Characteristic
Symbol IDDDR Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time Test Condition VDDS = 1.5V, E1S VDDS - 0.2V, VIN VDDS - 0.2V or VIN 0.2V 1.5 0 70 Min Typ Max Unit
3
10
3.3
A
V ns ns
VDR
tCDR tR
Note: 1. All other Inputs VIH VDDS -0.2V or VIL 0.2V. 2. Sampled only. Not 100% tested.
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APPENDIX A. BLOCK ADDRESS TABLES Table 25. Top Boot Block Addresses, M36W416TG
# 0 1 2 3 4 5 6 7 8 99 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
Table 26. Bottom Boot Block Addresses, M36W416BG
# 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
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APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data Table 27. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
structure is read from the memory. Tables 27, 28, 29, 30, 31 and 32 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 32, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode.
Note: Query data are always presented on the lowest order data outputs.
Table 28. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 88CEh 88CFh reserved 0051h 0052h 0059h 0003h 0000h 0035h Address for Primary Algorithm extended Query table (see Table 30) 0000h 0000h 0000h 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor specified algorithm supported (0000h means none exists) Address for Alternate Algorithm extended Query table (0000h means none exists) NA P = 35h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Query Unique ASCII String "QRY" Manufacturer Code Device Code Reserved "Q" "R" "Y" Intel compatible Description Value ST Top Bottom
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
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Table 29. CFI Query System Interface Information
Offset 1Bh Data 0027h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Typical time-out per single word program = 2n s Typical time-out for Double Word Program = 2n s Typical time-out per individual block erase = 2n ms Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2n times typical Maximum time-out for Double Word Program = 2n times typical Maximum time-out per individual block erase = 2n times typical Maximum time-out for chip erase = 2n times typical Value 2.7V
1Ch
0036h
3.6V
1Dh
00B4h
11.4V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C6h 0004h 0004h 000Ah 0000h 0005h 0005h 0003h 0000h
12.6V 16s 16s 1s NA 512s 512s 8s NA
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Table 30. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh M36W416TG 2Fh 30h 31h 32h 33h 34h 2Dh 2Eh M36W416BG 2Fh 30h 31h 32h 33h 34h Data 0015h 0001h 0000h 0002h 0000h 0002h 001Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0007h 0000h 0020h 0000h 001Eh 0000h 0000h 0001h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. Region 1 Information Number of identical-size erase block = 001Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Region 2 Information Number of identical-size erase block = 0007h+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical-size erase block = 001Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Value 2 MByte x16 Async. 4
2
31 64 KByte 8 8 KByte 8 8 KByte 31 64 KByte
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Table 31. Primary Algorithm-Specific Extended Query Table
Offset P = 35h (1) (P+0)h = 35h (P+1)h = 36h (P+2)h = 37h (P+3)h = 38h (P+4)h = 39h (P+5)h = 3Ah (P+6)h = 3Bh (P+7)h = 3Ch (P+8)h = 3Dh Data 0050h 0052h 0049h 0031h 0030h 0066h 0000h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit 0 Chip Erase supported (1 = Yes, 0 = No) bit 1 Suspend Erase supported (1 = Yes, 0 = No) bit 2 Suspend Program supported (1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Queued Erase supported (1 = Yes, 0 = No) bit 5 Instant individual block locking supported (1 = Yes, 0 = No) bit 6 Protection bits supported (1 = Yes, 0 = No) bit 7 Page mode read supported (1 = Yes, 0 = No) bit 8 Synchronous read supported (1 = Yes, 0 = No) bit 31 to 9 Reserved; undefined bits are `0' Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. Address (P+A)h contains less significant byte bit 0 Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' V DD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available. One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device unique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15 Lock/bytes JEDEC-plane physical high address bit 16 to 23 "n" such that 2n = factory pre-programmed bytes bit 24 to 31 "n" such that 2n = user programmable bytes Reserved Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0"
No Yes Yes No No Yes Yes No No
(P+9)h = 3Eh
0001h
Yes
(P+A)h = 3Fh (P+B)h = 40h
0003h 0000h
Yes Yes 3V
(P+C)h = 41h
0030h
(P+D)h = 42h
00C0h
12V
(P+E)h = 43h (P+F)h = 44h (P+10)h = 45h (P+11)h = 46h (P+12)h = 47h
0001h 0080h 0000h 0003h 0003h
01 80h 00h 8 Byte 8 Byte
(P+13)h = 48h
Note: 1. See Table 28, offset 15 for P pointer definition.
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Table 32. Security Code Area
Offset 80h 81h 82h 83h 84h 85h 86h 87h 88h Data 00XX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 64 bits: User Programmable OTP 64 bits: unique device number Protection Register Lock Description
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APPENDIX C. FLOWCHARTS AND PSEUDO CODES Figure 25. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* EF or GF must be toggled*/
Write Address & Data
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPPF Invalid Error (1, 2)
if (status_register.b3==1) /*VPPF invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI07919
Note: 1. Status check of b1 (Protected Block), b3 (V PPF Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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Figure 26. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* EF or GF must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPPF Invalid Error (1, 2)
if (status_register.b3==1) /*VPPF invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI07920
Note: 1. Status check of b1 (Protected Block), b3 (V PPF Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
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Figure 27. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* EF or GF must be toggled*/
Write B0h
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Program Complete
if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another address
} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } } Read Data
Write D0h
Write FFh
Program Continues
AI07921
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Figure 28. Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */
Write 20h
Write Block Address & D0h
Read Status Register
do { status_register=readFlash (any_address) ; /* EF or GF must be toggled*/
b7 = 1
NO } while (status_register.b7== 0) ;
YES b3 = 0 YES b4, b5 = 1 NO b5 = 0 YES b1 = 0 YES End }
AI07922
NO
VPPF Invalid Error (1)
if (status_register.b3==1) /*VPPF invalid error */ error_handler ( ) ;
YES
Command Sequence Error (1)
if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;
NO
Erase Error (1)
if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;
NO
Erase to Protected Block Error (1)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
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Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (any_address) ; /* EF or GF must be toggled*/
b7 = 1 YES b6 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Erase Complete
if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock else
} { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }
Write D0h
Write FFh
Erase Continues
Read Data
AI07923
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Figure 30. Locking Operations Flowchart and Pseudo Code
Start
Write 60h
locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (any_address, 0x90) ;
Write 01h, D0h or 2Fh
Write 90h
Read Block Lock States
Locking change confirmed? YES Write FFh
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ }
End
AI04364
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Figure 31. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ;
Write Address & Data
writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* EF or GF must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPPF Invalid Error (1, 2)
if (status_register.b3==1) /*VPPF invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI07924
Note: 1. Status check of b1 (Protected Block), b3 (V PPF Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE Table 33. Write State Machine Current/Next, sheet 1 of 2.
Current State Read Array Read Status Read Elect.Sg. Read CFI Query Lock Setup Lock Cmd Error Lock (complete) Prot. Prog. Setup Prot. Prog. (continue) Prot. Prog. (complete) Prog. Setup Program (continue) Prog. Sus Status Prog. Sus Read Array Prog. Sus Read Elect.Sg. Prog. Sus Read CFI Program (complete) Erase Setup Erase Cmd.Error Erase (continue) Erase Sus Read Sts Erase Sus Read Array Erase Sus Read Elect.Sg. Erase Sus Read CFI Erase (complete) SR bit 7 "1" "1" "1" "1" "1" "1" "1" "1" "0" "1" "1" "0" "1" "1" Data When Read Array Status Electronic Signature CFI Status Status Status Status Status Status Status Status Status Array Electronic Signature CFI Status Status Status Status Status Array Electronic Signature CFI Status Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Read Array Program (continue) Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Program Setup Erase Setup Erase (continue) Program (continue) Program (continue) Program (continue) Program (continue) Read Array Program Setup Command Input (and Next State) Read Array (FFh) Program Setup (10/40h) Program Setup Program Setup Program Setup Erase Setup (20h) Ers. Setup Erase Setup Erase Setup Erase Setup Lock (complete) Erase Confirm (D0h) Prog/Ers Suspend (B0h) Read Array Read Array Read Array Read Array Lock Cmd Error Read Array Read Array Protection Register Program Protection Register Program continue Erase Setup Read Array Program Prog. Sus Read Sts Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Read Array Erase CmdError Read Array Erase Sus Read Sts Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Read Array Erase (continue) Program (continue) Program (continue) Program (continue) Program (continue) Program (continue) Prog. Sus Read Sts Prog. Sus Read Sts Prog. Sus Read Sts Prog. Sus Read Sts Read Status Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Read Array Read Status Read Array Lock (complete) Prog/Ers Resume (D0h) Read Status (70h) Read Sts. Read Status Read Status Read Status Clear Status (50h) Read Array Read Array Read Array Read Array
Read Array Prog.Setup Read Array Read Array Read Array
Lock Command Error Read Array Read Array Program Setup Program Setup Erase Setup Erase Setup
Lock Command Error Read Status Read Status Read Array Read Array
"1"
"1" "1" "1" "1" "0" "1" "1"
Erase Command Error Read Array Program Setup Erase Setup
Erase Command Error Read Status Read Array
Erase (continue) Program Setup Program Setup Program Setup Program Setup Program Setup Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Setup
Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase Sus Erase Sus Read Sts Read Array Erase Sus Erase Sus Read Sts Read Array Erase Sus Erase Sus Read Sts Read Array Erase Sus Erase Sus Read Sts Read Array Read Status Read Array
"1"
"1" "1"
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
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Table 34. Write State Machine Current/Next, sheet 2 of 2.
Command Input (and Next State) Current State Read Elect.Sg. (90h) Read CFI Query (98h) Lock Setup (60h) Lock Setup Lock Setup Lock Setup Lock Setup Prot. Prog. Setup (C0h) Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Lock Confirm (01h) Lock Down Confirm (2Fh) Read Array Read Array Read Array Read Array Lock (complete) Read Array Read Array Unlock Confirm (D0h)
Read Array Read Status Read Elect.Sg.
Read Elect.Sg. Read CFI Query Read Elect.Sg. Read CFI Query Read Elect.Sg. Read CFI Query
Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup Lock Cmd Error Lock (complete) Prot. Prog. Setup Prot. Prog. (continue) Prot. Prog. (complete) Prog. Setup Program (continue) Prog. Suspend Read Status Prog. Suspend Read Array Prog. Suspend Read Elect.Sg. Prog. Suspend Read CFI Program (complete) Erase Setup Erase Cmd.Error Erase (continue) Erase Suspend Read Status Erase Suspend Read Array Erase Suspend Read Elect.Sg. Erase Suspend Erase Suspend Read Elect.Sg. Read CFI Query Erase Suspend Erase Suspend Read Elect.Sg. Read CFI Query Erase Suspend Erase Suspend Read Elect.Sg. Read CFI Query Read Elect.Sg. Read CFI Query Prog. Suspend Prog. Suspend Read Elect.Sg. Read CFI Query Prog. Suspend Prog. Suspend Read Elect.Sg. Read CFI Query Prog. Suspend Prog. Suspend Read Elect.Sg. Read CFI Query Prog. Suspend Prog. Suspend Read Elect.Sg. Read CFI Query Read Elect.Sg. Read CFIQuery Read Elect.Sg. Read CFI Query
Lock Command Error Read Elect.Sg. Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup Lock Setup
Protection Register Program Protection Register Program (continue) Lock Setup Prot. Prog. Setup Program Program (continue) Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Lock Setup Prot. Prog. Setup Read Array Erase (continue) Read Array Program (continue) Program (continue) Program (continue) Program (continue) Read Array
Erase Command Error Lock Setup Prot. Prog. Setup Erase (continue) Lock Setup Lock Setup Lock Setup Lock Setup Lock Setup Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Prot. Prog. Setup Read Array
Erase (continue) Erase (continue) Erase (continue) Erase (continue)
Erase Suspend Erase Suspend Erase Suspend Read CFI Query Read Elect.Sg. Read CFI Query Erase (complete) Read Elect.Sg. Read CFI Query
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
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REVISION HISTORY Table 35. Document Revision History
Date 19-Nov-2002 Version 1.0 First Issue Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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